The present invention relates generally to a dynamic random access memory (DRAM) device and, more particularly, to a vertical DRAM device having robust gate-to-storage node isolation.
In the semiconductor industry, there is an ever-increasing desire to increase memory density and performance. These goals are often achieved by scaling dynamic random access memory (DRAM) devices to smaller dimensions and operating voltages.
A DRAM cell may include a horizontal, planar, MOSFET (metal oxide semiconductor field effect transistor) transfer device coupled to a deep trench storage capacitor by a buried strap. As the size of such a DRAM cell is scaled to increase memory density, scaling of the channel length of the transfer device may be limited to prevent degradation of sub-threshold leakage requirements (or retention time requirements).
Vertical memory devices, which use a trench to form both a signal storage node and a signal transfer device, have been proposed to increase memory density. Vertical memory devices may have degrading performance due to storage node leakage.
To overcome the shortcomings of conventional DRAM devices, a new DRAM device is provided. An object of the present invention is to provide a DRAM device that has improved charge retention characteristics. A related object is to provide a process of manufacturing such a DRAM device. Another object is to provide a process of manufacturing such a DRAM device which is compatible with manufacturing support circuitry.
To achieve these and other objects, and in view of its purposes, the present invention provides a dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator. The gate insulator thickness is less than the trench-top dielectric thickness.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.